With increase of integration in semiconductor memory devices, a working speed thereof has also been improved. Synchronous memory devices, which operate in synchronization with an external clock signal from an external circuit, have been developed in order to improve the operating speed.
SDR (single data rate) synchronous memory devices, in which data are output through data pads in synchronization with a rising edge of a clock signal, were first proposed.
However, SDR synchronous memory devices are not sufficient to satisfy the required performance in the high-speed system. Accordingly, DDR (double data rate) synchronous memory devices have been proposed. In DDR synchronous memory devices, data are output through data pads in synchronization with rising and falling edges of a clock signal.
Since two data are sequentially output through data pads in synchronization with both a rising edge and a falling edge of a clock signal from an external circuit in DDR (double data rate) synchronous memory devices, band width of data in DDR synchronous memory devices can be as wide as twice that of SDR synchronous memory devices so that the DDR synchronous memory devices make it possible to implement a high-speed operation.
However, since DDR synchronous memory devices receive and output two data within one period of a clock signal, an access method which has been used in SDR synchronous memory devices cannot be applied effectively to DDR synchronous memory devices.
When the period of a clock signal is approximately 10 nsec, the two data have to be processed below 6 nsec, when the rising and falling time (about 0.5×4=2) and other requirements prescribed in the specification are considered. This processing is not sufficiently carried out in the memory devices. Accordingly, the memory devices receive and output the data in synchronization with the rising and falling edges of the clock signal when the data are input and output from and to an external circuit; however, the data are actually processed in synchronization with only one of the rising and falling edges of the clock signal within the memory device.
Accordingly, a new data I/O (input/output) method is required when the memory device transfers the received data to an inner core region or the memory device transfers the data from the inner core region to an external circuit.
To achieve this I/O method, a data input buffer of the DDR memory device prefetches and aligns two- or four-bit data which are in synchronization with the rising and falling edges of the clock signal and then transfers odd or even data to the inner core region in synchronization with a rising edge of a main clock signal.
Meanwhile, in order to inform a CUP (control unit and processor) or a memory controller of the exact timing of the output data, the memory chip outputs a data strobe signal DQS and an inverted data strobe signal /DQS together with the data signal DQ.
Since the data strobe signal DQS and the inverted data strobe signal /DQS lead the data signal DQ by one clock cycle in the DDR memory device, they are output in synchronization with the clock signal, which is used as the synchronization signal of the data signal DQ, after the data signal DQ is output and a preamble time (tRPRE, Read DQS Preamble time) is ensured.
In the preamble time (or section), the data signal DQ is in a Hi-z state (a half level (½) of a supply voltage), the data strobe signal DQS is at a low level, and the inverted data strobe signal /DQS is at a high level.
The data signal DQ, which is in a Hi-z state, obtains a valid data window faster than the data strobe signal DQS and the inverted data strobe signal /DQS after the termination of the preamble time. The first valid data window of the data signal DQ, which is output after the termination of the preamble time, is wider than that of the data strobe signal DQS and the inverted data strobe signal /DQS. Since the second valid data window is wider than the first valid data window in the data strobe signal DQS and the inverted data strobe signal /DQS, the data eye of the data strobe signal DQS and the inverted data strobe signal /DQS cannot be formed evenly. Particularly, this is conspicuous at a high frequency operation so that the reliability of the semiconductor memory device deteriorates at the high frequency operation.